1. Field of the Invention
The present invention relates to a protection transistor, more specifically to a metal-oxide-semiconductor transistor for protecting a semiconductor device from electrostatic damage.
2. Description of the Related Art
Developments in semiconductor fine-patterning technology have increased the integration density and speed of large-scale integrated (LSI) circuits. Recently there has been much interest in silicon-on-insulator (SOI) devices, which combine high speed with low power dissipation. In an SOI device, a thin silicon layer, about five hundred angstroms (500 xc3x85) thick, is formed on a buried oxide (BOX) layer. Circuit elements such as metal-oxide-semiconductor (MOS) transistors formed in the silicon layer are electrically isolated by the BOX layer and by a field oxide formed in the semiconductor layer.
This complete isolation reduces the parasitic capacitance of MOS transistors formed in an SOI device, and the thinness of the silicon layer enables complete or nearly complete channel depletion to be attained, resulting in a sharp operating characteristic. These are the reasons for the low power dissipation and high speed. From the standpoint of reliability, a further advantage is that latch-up does not occur, because no parasitic bipolar transistors are formed. The structure of the MOS transistors in an SOI device, however, places small junction areas in the thin silicon layer, making the MOS transistors extremely vulnerable to thermal damage from current surges caused by electrostatic discharge. Preventing such damage is a key issue in SOI technology.
A known way to protect a semiconductor device from electrostatic discharge is to provide the device with internal protection transistors coupled to its input and output terminals. The protection transistors are MOS transistors that are permanently turned off by interconnection of their source and gate electrodes, but they are designed to be capable of conducting substantial amounts of breakdown current. If an electrostatic surge enters the device at an input or output terminal, the protection transistor breaks down, and the surge current escapes through the protection transistor to ground or the power supply, thereby preventing damage to the device.
The layout of an NMOS (n-channel MOS) transistor in an SOI device is shown in top plan view in FIG. 6A. FIG. 6B is a cross-sectional view through line A-B in FIG. 6A, and FIG. 6C is a cross-sectional view through line C-D in FIG. 6A. The NMOS transistor is formed in an active region 200 having edge areas 200E. The active region 200 includes a pair of n-type diffusion layers 201 formed by diffusion or implantation of an n-type impurity, followed by the formation of a salicide (self-aligned silicide) layer 201M. The n-type diffusion layers 201 include a source diffusion and a drain diffusion, disposed on either side of a p-type body region 202. The p-type body region 202 is disposed below a gate electrode 203, which is insulated from the p-type body region 202 by a gate oxide film 207. An n-type channel forms in the body region 202 when an appropriate voltage is applied to the gate electrode 203. The active region 200 is surrounded by an inactive region 205 comprising a field oxide layer. The active region 200 and inactive region 205 are underlain by a buried oxide (BOX) layer 206, and are covered by an interlayer dielectric film 208. Source and drain electrodes (not shown) make contact with the n-type diffusion layers 201 through two rows of contact holes 204 in the interlayer dielectric film 208.
An example of the layout of a conventional NMOS protection transistor in an SOI device is shown in top plan view in FIG. 7A. FIG. 7B is a cross-sectional view through line A-B in FIG. 7A, and FIG. 7C is a cross-sectional view through line C-D in FIG. 7A. The NMOS protection transistor is formed in an active region 100 having edge areas 100E. The active region 100 includes a pair of n-type diffusion layers 101, forming a source diffusion and a drain diffusion, disposed on either side of a p-type body region 102, in which the channel of the transistor is formed. The p-type body region 102 is disposed beneath a gate electrode 103. Source and drain electrodes (not shown) make contact with the n-type diffusion layers 101 through two rows of contact holes 104 in an interlayer dielectric film 108. A silicide layer 101M is formed in the n-type diffusion layers 101 beneath each row of contact holes 104. The active region 100 is surrounded by an inactive region 105 formed by a field oxide layer, and is underlain by a BOX layer 106. A gate oxide film 107 insulates the gate electrode 103 from the p-type body region 102.
A problem known as the subthreshold hump appears in MOS transistors in an SOI device. The process of isolating the circuit elements creates an extremely thinned silicon layer in the edge areas 200E of the n-type diffusion layer 201 and p-type body region 202, so the threshold voltage becomes lower in the edge areas 200E than in the interior part of the active region 200. The subthreshold operating characteristic therefore departs from a continuous smooth curve and leakage current in the off-state is increased.
An example of this hump effect in the NMOS transistor shown in FIGS. 6A to 6C is illustrated by the current-voltage operating characteristics in FIG. 8A, and by the curve in FIG. 8B, which shows the dependence of the threshold voltage in the edge areas of the active region on the gate width, shown in micrometers (xcexcm). In FIG. 8A, curve S is the operating characteristic of an NMOS transistor without a hump component, and curve SH is the operating characteristic when a hump is present.
As shown in FIG. 6B, the field oxide film formed in the inactive region 205 in the circuit element isolation process projects into the active region 200, thinning the silicon layer in the edge areas 200E. The projecting oxide is also thinned, by over-etching of a pad oxide film that is formed and removed during the fabrication process. In the edge areas 200E, accordingly, the p-type body region 202 is easily depleted when biased by the gate electrode, and the threshold voltage for channel formation in the edge areas 200E is lowered. The subthreshold operating characteristic of the NMOS transistor is therefore shifted from the hump-free curve S in FIG. 8A to the humped curve SH, increasing the off-state leakage current. The narrower the width of the gate electrodes is, the lower the threshold voltage at the edges of the active region becomes, as shown in FIG. 8B, so in an NMOS transistor with a narrow gate, the hump comes to dominate the subthreshold operating characteristic.
A technique commonly used to prevent this hump effect is the implantation of a channel stop to raise the threshold voltage at the edges of the active region. In this technique, ions are implanted in the edge areas of the active region, near the edges of the source diffusion, the drain diffusion, and the body region of the transistor. The implanted ions are of the same conductive type as the body region and differ from the conductive type of the source diffusion and the drain diffusion; usually, boron is implanted in an NMOS transistor and phosphorus in a PMOS (p-channel MOS) transistor. This channel stop implantation increases the impurity density in the body region near the edges of the active region, making the edge areas of the body region harder to deplete, thus raising the threshold voltage at the edges of the active region and preventing the hump effect.
The formation of a metal-silicide layer on the source and drain diffusions, (e.g., the salicide layer 201M in FIGS. 6A and 6C) is a technique commonly used to reduce the resistance of the source and drain diffusions of a MOS transistor in an SOI device. A salicide layer is a metal-silicide layer that is formed on the source and drain diffusion layers in self-alignment with the gate electrode. Metal-silicide has relatively high conductivity, so the formation of self-aligned silicide layers on the source and drain diffusion layers reduces their resistance.
In the NMOS protection transistor in FIG. 7A, as in the NMOS transistor in FIG. 6A, the silicon layer is thinned in the edge areas 100E of the n-type diffusion layers 101 and the p-type body region 102 (see FIG. 7B), so a channel stop implantation is carried out. In the NMOS protection transistor in FIG. 7A, however, the silicide layer 101M is formed on the n-type diffusion layers 101 only beneath the rows of contact holes 104, instead of being self-aligned with the gate electrode as in the NMOS transistor in FIG. 6A. A non-silicided part of the n-type diffusion layer 101 is thus left between the silicide layer 101M and the p-type body region 102 disposed beneath the gate electrode 103. The reason for leaving this non-silicided area is to avoid having electrostatic discharge current surge across the low-resistance surface interface of the silicon layer, since that would decrease the effective junction area in which breakdown could occur and thus reduce the electrostatic damage protection performance of the protection transistor.
In this conventional protection transistor, however, there is a problem in that the protection transistor itself can easily be damaged by electrostatic surges, due to thermal damage at the edges of the active region. Since the channel stop implantation increases the impurity density in the edge areas of the body region of the protection transistor, although the threshold voltage in these areas is increased, the breakdown voltage is reduced. Consequently, when an electrostatic surge occurs, the outer parts of the active region break down before the interior part, concentrating surge current into the circled areas 110 in FIG. 7A, at the edges of the active region 110 between the silicide layers 101M. That is, these edge areas 110 respond faster than the interior part of the active region 100 to the electrostatic surge. The silicon layer at the edges of the active region is thin and the junction area there is small, so the concentrated surge current can easily cause thermal damage in the circled areas 110.
An object of the present invention is to provide a protection transistor that offers improved protection from electrostatic damage by avoiding the concentration of breakdown current at the edges of the active region.
The invented protection transistor is an MOS transistor having source and drain diffusion layers of a first conductive type formed in an active region in a semiconductor layer. Between the source and drain diffusion layers there is a body region of a second conductive type, which is disposed below a gate electrode.
According to a first aspect of the invention, the semiconductor layer is covered by a dielectric layer having rows of contact holes disposed above the source and drain diffusion layers. A silicide layer is formed in two strips on the source and drain diffusion layers, one strip disposed below each row of contact holes. The silicide layers are separated from the gate electrode by a greater distance in the edge areas of the active region than in the interior part of the active region. The increased separation increases the breakdown voltage at the edges of the active region, thereby reducing the flow of breakdown current at the edges of the active region.
According to a second aspect of the invention, the gate length of the gate electrode is longer in the edge areas of the active region than in the interior part of the active region. The longer gate length also increases the breakdown voltage and reduces the flow of breakdown current at the edges of the active region.
According to a third aspect of the invention, the semiconductor layer is covered by a dielectric layer having rows of contact holes as described above. The active region is wider beneath the gate electrode than beneath the two rows of contact holes. The edges of the body region thus project beyond the edges of the diffusion layers adjacent the rows of contact holes. This increases the breakdown voltage and reduces the flow of breakdown current in the edge areas of the body region, by moving these areas farther away from the rows of contact holes. The gate length of the gate electrode may also be longer in the edge areas of the active region than in the interior part of the active region.